The present invention relates to system time reference recovery devices, recovery systems and methods. More specifically, the present invention relates to such recovery devices, recovery systems and recovery methods for audio/visual decoders (alternatively referred to as “A/V decoders”), where the A/V decoders are adapted to process, decode or decompress input data streams (alternatively referred to as “input data”, “input data streams” or “data streams”) that are coded or compressed using a compression format.
Currently, a plurality of formats or techniques is used to compress audio-video programs for transmission and storage. See, for example, the compression standards set forth in ISO/IEC 13818-1,2,3: Information Technology-Generic Coding of Moving Pictures and Associated Audio Information: Systems, Video and Audio (alternatively referred to as “MPEG-2”) including Annex D thereof (alternatively referred to as “Annex D”); ISO/IEC 11172-1,2,3: Information Technology-Generic Coding of Moving Pictures and Associated Audio for Digital Storage Media at up to about 1.5 Mbits/sec: Systems, Video and Audio (alternatively referred to as “MPEG-1”); Dolby AC-3; Motion JPEG, etc, each of which is incorporated herein by reference in its entirety.
Currently available A/V decoders generally include one or more clock devices. These clock devices ensure that the output of the audio and video samples, data or other information (collectively referred to as “data”) is output at the same rate the data is received and input into the A/V decoder. For example, currently available A/V decoders are based on MPEG-2 transport of data. To ensure proper operation of such A/V decoders (and any larger A/V system incorporating such A/V decoders) the data output rate of the A/V decoder must match the data input rate of the A/V decoder to prevent overflow or underflow of the A/V decoders' buffers. This means that the output video frame rate of the A/V decoder must match its compressed input frame rate and the output audio sample rate of the A/V decoder must match its compressed input audio sample rate.
To accomplish such synchronization in an A/V system, MPEG-2 transport synchronizes the transmitter (the headend in an A/V system for example) and the receiver (the A/V decoder in an A/V system for example) using a system time clock (alternatively referred to as an “STC” and which may comprise a common 27 MHz clock for example). Further, the transmitter transmits or communicates one or more program clock references (alternatively referred to as “PCR”) to the receiver. The receiver uses the one or more PCRs to synchronize itself with the transmitter.
Such synchronization in the A/V system may be accomplished using a phase-locked loop (alternatively referred to as a “PLL”). Typically the receivers include a local clock (for example, a voltage-controlled oscillator, alternatively referred to as a “VCO”). The receiver compares its local clock to the PCR. If the receiver's local clock is slower than or behind the PCR, the receiver accelerates the local clock. If the receiver's local clock is faster than or ahead of the PCR, the receiver decelerates the local clock. It is contemplated that eventually, the receiver's local clock is synchronized with the STC. Subsequently, the MPEG transport synchronizes the video and audio to the STC. It is further contemplated that most video and audio frames include a presentation time stamp (alternatively referred to as “PTS”) and/or a decode time stamp (alternatively referred to as “DTS”). The receiver (the AN decoder for example) may use such PTS and/or DTS stamps to determine when to decode and display each frame relative to the STC.
It is further contemplated that the local clock (the VCO for example) is used to clock one or more audio/video digital-to-analog converters (alternatively referred to as “DACs”) in the A/V decoders. Using the local clock to clock the one or more DACS ultimately determines the video frame rate and audio sample rate at the output of the A/V decoder. Since the local clock is locked to the STC, the output rates of the A/V decoder are thus locked to the transmitter.
However, A/V systems are growing more complex, requiring that AN decoders integrate more features. A complex A/V decoder may decode several streams simultaneously, requiring several different local clocks. For example one set-top box including a decoder may support two televisions. Each television may display different programs. It is contemplated that each television may be able to support picture-in-picture (alternatively referred to as “PIP”), such that each television may display two different programs simultaneously. In this example, the set-top box may also decode another program to record for future playback. It is contemplated that different local clocks are used to clock all these programs. Furthermore, a complex A/V decoder may require additional synchronous clocks for DRAM and/or internal interfaces (DVI, Ethernet and USB for example).
Typically, existing A/V decoders rely on VCOs for AV decoding and processing. Advanced A/V decoders with picture-in-picture or PIP or multiple displays may require several VCOs. However, high quality VCOs are expensive. Using a plurality of VCOs in the A/V decoder will affect its production costs and ultimately its retail price. It is contemplated that using multiple clocks (e.g., VCOs) may complicate decoder design. For example, clock balancing, static timing analysis and asynchronous data transfer in the A/V decoder are all affected by multiple clocks. Further, it is known that currently available VCOs may lock to other system clocks (which is sometimes referred to as “injection locking”). Therefore, using multiple VCOs in an A/V decoder may cause such VOC to become locked, ultimately affecting the performance of the A/V decoders.
VCOs are analog components. This means that performance of each VCO may vary depending on the temperature, process and manufacturer. This variance makes designing A/V decoders using such VCOs difficult. Additionally, sharing hardware (video scaler for example) in the A/V decoder is difficult, if such hardware is run at the STC clock rate.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.